In some applications, power consumption by a processor is an important consideration. For instance, power consumption may be a significant concern in Customer Premises Equipment (CPE) for an Advanced Digital Subscriber Line (ADSL) communications link Dowered through a Universal Serial Bus (USB) connection, where the power available through the USB connection is constrained.
Apart from low power design techniques employed at the circuit level, runtime power saving within processors has been addressed through either frequency/voltage scaling or circuit shutdown. Both approaches rely on monitoring circuits and control software added to the processor to collect runtime information and identify idle periods in processor activity during which any change is triggered. Transmeta LongRun and Intel SpeedStep are examples of voltage/frequency scaling adopted in commercial processors.
In such systems, the monitoring activity necessary to perform the dynamic analysis represents a hardware and software overhead, consuming silicon area, processor cycles and program memory, and itself contributing to the overall processor power dissipation.
There is, therefore, a need in the art for a voltage and/or clock frequency scaling technology for a programmable platform that inherently gives power optimization gains without requiring the addition of monitoring circuitry and software.